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NXP Semiconductors /LPC43xx /USB0 /ENDPTSTAT

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Interpret as ENDPTSTAT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ERBR0)ERBR0 0 (ERBR1)ERBR1 0 (ERBR2)ERBR2 0 (ERBR3)ERBR3 0 (ERBR4)ERBR4 0 (ERBR5)ERBR5 0RESERVED0 (ETBR0)ETBR0 0 (ETBR1)ETBR1 0 (ETBR2)ETBR2 0 (ETBR3)ETBR3 0 (ETBR4)ETBR4 0 (ETBR5)ETBR5 0RESERVED

Description

Endpoint status

Fields

ERBR0

Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 … ERBR5 = endpoint 5
ERBR1

Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 … ERBR5 = endpoint 5
ERBR2

Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 … ERBR5 = endpoint 5
ERBR3

Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 … ERBR5 = endpoint 5
ERBR4

Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 … ERBR5 = endpoint 5
ERBR5

Endpoint receive buffer ready for physical OUT endpoints 5 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ERBR0 = endpoint 0 … ERBR5 = endpoint 5
RESERVED

reserved
ETBR0

Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 … ETBR5 = endpoint 5
ETBR1

Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 … ETBR5 = endpoint 5
ETBR2

Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 … ETBR5 = endpoint 5
ETBR3

Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 … ETBR5 = endpoint 5
ETBR4

Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 … ETBR5 = endpoint 5
ETBR5

Endpoint transmit buffer ready for physical IN endpoints 3 to 0. This bit is set to 1 by hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. ETBR0 = endpoint 0 … ETBR5 = endpoint 5
RESERVED

reserved

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data